{"id":83,"date":"2026-06-21T12:13:50","date_gmt":"2026-06-21T12:13:50","guid":{"rendered":"https:\/\/genuineenabling.com\/?p=83"},"modified":"2026-06-21T12:13:50","modified_gmt":"2026-06-21T12:13:50","slug":"technical-background-page","status":"publish","type":"post","link":"https:\/\/genuineenabling.com\/?p=83","title":{"rendered":"TECHNICAL BACKGROUND PAGE"},"content":{"rendered":"\n


Technical Background \u2014 The \u2019730 Patent and Logic\u2011Design Structure<\/h2>\n\n\n\n
    \n
  1. Overview of the Invention<\/strong>\n
      \n
    • U.S. Patent No. 6,219,730 discloses a logic\u2011design structure<\/strong>\u2014identified in the specification as Block 34<\/strong>\u2014that performs the dual function<\/strong> of:\n
        \n
      • synchronizing two data streams, and<\/li>\n\n\n\n
      • encoding those streams into a unified framed output, all under control of a bit\u2011rate clock (BCLK)<\/strong>.<\/li>\n<\/ul>\n<\/li>\n\n\n\n
      • The patent illustrates one implementation of this structure using a gate\u2011level example<\/strong> (Figure 4A). This example shows how the dual function can be realized using standard logic elements such as flip\u2011flops, a selector, and timing signals.<\/li>\n<\/ul>\n<\/li>\n\n\n\n
      • Gate\u2011Level Example vs. POSITA Implementation<\/strong>\n
          \n
        • A person of ordinary skill in the art (POSITA) would understand that the gate\u2011level depiction in Figure 4A is one disclosed embodiment<\/strong>, not a limitation.<\/li>\n\n\n\n
        • A POSITA could implement the same dual\u2011function structure using well\u2011known integrated\u2011circuit (IC) technologies, including:\n
            \n
          • ASICs<\/li>\n\n\n\n
          • gate arrays<\/li>\n\n\n\n
          • programmable logic devices (CPLDs, FPGAs)<\/li>\n\n\n\n
          • microcontroller\u2011based logic<\/li>\n\n\n\n
          • VLSI logic blocks<\/li>\n<\/ul>\n<\/li>\n\n\n\n
          • These implementations may differ in their internal circuitry, yet a POSITA would recognize them as corresponding structures because they perform the recited dual function as a unified whole, consistent with the specification and without requiring any imported, irrelevant limitations.<\/li>\n\n\n\n
          • This engineering flexibility is fundamental to logic\u2011design practice.<\/li>\n<\/ul>\n<\/li>\n\n\n\n
          • Why the Dual Function Matters<\/strong>\n
              \n
            • The claim recites a single, inseparable dual function<\/strong>:\n
                \n
              • synchronizing and encoding<\/strong> (two data streams under control of a bit\u2011rate clock)<\/li>\n<\/ul>\n<\/li>\n\n\n\n
              • A POSITA understands that synchronization and encoding are coordinated operations governed by the same timing signals.<\/li>\n\n\n\n
              • This is why the PTAB and the Western District of Washington recognized Block 34 as a complete, enabled structure<\/strong>.<\/li>\n<\/ul>\n<\/li>\n\n\n\n
              • Timing Behavior (Figure 4B)<\/strong>\n
                  \n
                • Figure 4B illustrates the timing relationships among:\n
                    \n
                  • the bit\u2011rate clock (BCLK)<\/li>\n\n\n\n
                  • the selector signal (SEL)<\/li>\n\n\n\n
                  • the frame\u2011start signal (FS)<\/li>\n\n\n\n
                  • the output bits (QH)<\/li>\n<\/ul>\n<\/li>\n\n\n\n
                  • These timing diagrams show how the logic\u2011design structure aligns the two input streams, inserts framing bits, and produces a unified output stream.<\/li>\n<\/ul>\n<\/li>\n\n\n\n
                  • How \u00a7112(f) Relates to the Technical Structure<\/strong>\n
                      \n
                    • Under \u00a7112(f), the analysis requires:\n
                        \n
                      • identifying the claimed function<\/strong>,<\/li>\n\n\n\n
                      • identifying the corresponding structure<\/strong>, and<\/li>\n\n\n\n
                      • determining equivalents<\/strong> of that structure.<\/li>\n<\/ul>\n<\/li>\n\n\n\n
                      • For the \u2019730 patent:\n
                          \n
                        • the function<\/strong> is the dual function of synchronizing and encoding,<\/li>\n\n\n\n
                        • the corresponding structure<\/strong> is the logic\u2011design block (Block 34), and<\/li>\n\n\n\n
                        • equivalent structures<\/strong> include any IC implementation that performs the same dual function in the same overall way.<\/li>\n<\/ul>\n<\/li>\n\n\n\n
                        • A POSITA would not treat the gate\u2011level example as limiting. <\/li>\n\n\n\n
                        • They would recognize that the invention can be implemented using many IC technologies.<\/li>\n<\/ul>\n<\/li>\n\n\n\n
                        • Why the Technical Background Matters for the Case<\/strong>\n
                            \n
                          • Understanding the technical structure clarifies why the lower courts erred when they:\n
                              \n
                            • isolated only the \u201csynchronizing\u201d portion of the dual function,<\/li>\n\n\n\n
                            • imported additional components not tied to the claim,<\/li>\n\n\n\n
                            • demanded gate\u2011level detail, and<\/li>\n\n\n\n
                            • refused to evaluate the structure as a whole.
                              <\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ol>\n\n\n\n

                              <\/p>\n","protected":false},"excerpt":{"rendered":"

                              Technical Background \u2014 The \u2019730 Patent and Logic\u2011Design Structure<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-83","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"brizy_media":[],"_links":{"self":[{"href":"https:\/\/genuineenabling.com\/index.php?rest_route=\/wp\/v2\/posts\/83","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/genuineenabling.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/genuineenabling.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/genuineenabling.com\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/genuineenabling.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=83"}],"version-history":[{"count":2,"href":"https:\/\/genuineenabling.com\/index.php?rest_route=\/wp\/v2\/posts\/83\/revisions"}],"predecessor-version":[{"id":85,"href":"https:\/\/genuineenabling.com\/index.php?rest_route=\/wp\/v2\/posts\/83\/revisions\/85"}],"wp:attachment":[{"href":"https:\/\/genuineenabling.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=83"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/genuineenabling.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=83"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/genuineenabling.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=83"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}