Title: Case Summary — GET LLC v. Sony & Nintendo

Overview

Genuine Enabling Technology LLC (GET) owns U.S. Patent No. 6,219,730, which discloses a logic‑design structure that implements the dual function of synchronizing and encoding two data streams under control of a bit‑rate clock. A person of ordinary skill in the art (POSITA) would implement this structure using standard integrated‑circuit (IC) technologies—including ASICs, gate arrays, programmable logic devices, or microcontroller‑based logic—rather than being limited to the gate‑level example depicted in the ’730 patent. The invention is broadly applicable to modern controllers and wireless communication modules.

GET brought infringement actions against Sony and Nintendo in separate district courts.

• Sony (District of Delaware): The court granted summary judgment of non‑infringement, and the Federal Circuit affirmed.
• Nintendo (Western District of Washington): The court reached a different conclusion, issuing an order recognizing that the disclosed logic‑design block (Block 34) is a complete, enabled structure understood by a POSITA and rejecting Nintendo’s indefiniteness challenge.

Three PTAB panels likewise recognized the same structure when denying the IPR petitions filed by Sony and Nintendo.

The Central Legal Issue

This case presents a fundamental question under 35 U.S.C. §112(f):

May courts require a Function‑Way‑Result (FWR) analysis as a threshold to literal infringement under §112(f), demanding enumeration of internal “ways” and gate‑level details before allowing any structural comparison?

The lower courts answered “yes.”

Supreme Court precedent and Federal Circuit precedent say “no.”

Why the Lower Courts Erred

The lower courts committed a fundamental legal error in their application of 35 U.S.C. §112(f). Rather than identifying the corresponding structure tied to the dual function recited in the claim and evaluating that structure as a whole, the courts

1. Misidentified the corresponding structure by isolating only the “synchronizing” portion of the dual function.
   • The claim recites a single, inseparable dual function—synchronizing and encoding two data streams.
   • The courts treated “synchronizing” as if it were a standalone function, contrary to the claim language and §112(f)’s requirement that the function be taken as recited.
2. Expanded the “synchronizing” function by importing additional components not tied to the claimed function.
   • The courts treated the oscillator, clock generator, and flip‑flops as if they were required elements of the claimed function, even though:
     • the claim does not recite them,
     • the specification does not require them, and
     • the PTAB and the Western District of Washington rejected this interpretation.
   • This expansion altered the statutory function and distorted the corresponding structure.
3. Faulted GET for not analyzing the “ways” of these extra components—components that do not belong to the claimed function.
   • Because the courts misidentified the structure, they then blamed GET for not performing a Function‑Way‑Result analysis on components that §112(f) does not require to be part of the corresponding structure.
   • This reverses the statutory sequence.
4. Demanded gate‑level detail and internal “ways” before allowing any structural comparison.
   • The courts required GET to enumerate:
     • the “way” of each internal element,
     • the “way” of the accused structure, and
     • gate‑level circuitry not disclosed in the patent.
   • This is a mechanical dissection approach that Odetics expressly forbids.
5. Refused to evaluate the actual corresponding structure as a whole.
   • Odetics requires evaluating:
     • the disclosed structure as a whole, at the level of detail the patent provides
   • The courts did not evaluate the disclosed logic‑design block (Block 34) as a whole. Instead, they:
     • isolated sub‑functions,
     • imported extra components,
     • demanded internal “ways,” and
     • used the absence of this improper analysis to deny literal infringement.
6. Used Function‑Way‑Result (FWR) as a threshold gatekeeper, not a comparison tool.
   • Instead of applying FWR only at the final step of §112(f) to compare the disclosed structure with the accused structure, the courts used FWR as a preliminary requirement in the structural analysis itself. This inverted the statutory sequence, collapsed §112(f) into the doctrine of equivalents, and contradicted:
     • Graver Tank
     • Warner‑Jenkinson
     • Odetics
     • WMS Gaming
7. Why the Issue Matters
   • If allowed to stand, this doctrinal drift would:
     • Eliminate the statutory pathway for literal infringement
     • Force patentees to disclose gate‑level circuitry for logic‑design inventions
     • Undermine the engineering discipline of logic design
     • Create inconsistent outcomes between tribunals
     • Narrow §112(f) to the point of practical extinction

Procedural Posture

• Federal Circuit judgment entered
• Cert petition deadline: July 22, 2026
• Document repository available July 3, 2026