GET LLC v. Sony & Nintendo — Statutory §112(f), DOE/FWR, and the Doctrinal Inversion

Overview

Genuine Enabling Technology LLC (GET) owns U.S. Patent No. 6,219,730, which discloses a logic‑design structure that performs a single, inseparable dual function:

• synchronizing two data streams, and
• encoding them under control of a bit‑rate clock.

A person of ordinary skill in the art (POSITA) would implement this functional block using standard integrated‑circuit (IC) technologies—ASICs, gate arrays, programmable logic devices, or microcontroller‑based logic—not by reproducing the gate‑level example shown in the patent. The invention is broadly applicable to modern controllers and wireless communication modules.

GET brought infringement actions against Sony and Nintendo in separate district courts:

• Sony (D. Del.) — summary judgment of non‑infringement; affirmed by the Federal Circuit.
• Nintendo (W.D. Wash.) — the court recognized that the disclosed logic‑design block (Block 34) is a complete, enabled structure understood by a POSITA and rejected Nintendo’s indefiniteness challenge.

Three PTAB panels likewise recognized the same structure when denying IPR petitions filed by Sony and Nintendo.

The Central Legal Issue

This case presents a fundamental question under 35 U.S.C. §112(f):

May courts import the doctrine of equivalents and the Function‑Way‑Result test into the statutory §112(f) claim‑construction stage, thereby requiring a “way‑by‑which” analysis and gate‑level detail before allowing any structural comparison?

The lower courts effectively answered yes. The statute, Supreme Court precedent, and Federal Circuit precedent say no.

The Doctrinal Inversion

By importing DOE and the Function‑Way‑Result test into the statutory §112(f) claim‑construction stage, the lower courts inverted the required sequence of analysis and effectively prevented the patentee from presenting infringement at the fact‑finding trial stage — the only stage where DOE/FWR properly applies and where factual determinations of equivalence or potential copying can be made.

This inversion is the root cause of every downstream error.

Where the Lower Courts Went Wrong

The lower courts departed from the statutory framework in seven ways. Each error is a symptom of the same doctrinal inversion.

1. Misidentifying the Statutory Function

The claim recites a single dual function: synchronizing and encoding two data streams.

The courts isolated only “synchronizing,” treating it as a standalone function. §112(f) requires using the function as recited, not a judicially narrowed version.

2. Expanding the Function by Importing Extra Components

The courts treated the oscillator, clock generator, and flip‑flops as if they were required elements of the claimed function—even though:

• the claim does not recite them,
• the specification does not require them, and
• the PTAB and W.D. Wash. rejected this interpretation.

This expansion distorted both the statutory function and the corresponding structure.

3. Faulting GET for Not Analyzing “Ways” of Components Outside the Function

Because the courts misidentified the structure, they then faulted GET for not performing a Function‑Way‑Result analysis on components that do not belong to the corresponding structure under §112(f).

This reverses the statutory sequence.

4. Demanding Gate‑Level Detail and Internal “Ways” Before Allowing Structural Comparison

The courts required GET to enumerate:

• the “way” of each internal element,
• the “way” of the accused structure,
• gate‑level circuitry not disclosed in the patent.

This is the mechanical dissection approach that Odetics expressly forbids.

5. Refusing to Evaluate the Corresponding Structure as a Whole

Odetics requires evaluating:

• the disclosed structure as a whole,
• at the level of detail the patent provides.

The courts did not evaluate the disclosed logic‑design block (Block 34) as a whole. Instead, they:

• isolated sub‑functions,
• imported extra components,
• demanded internal “ways,”
• and used the absence of this improper analysis to deny literal infringement.

6. Using FWR as a Gatekeeper Instead of a Comparison Tool

DOE’s Function‑Way‑Result test is a judicial infringement doctrine, not a claim‑construction tool. It belongs at trial, not at claim construction.

By using FWR as a threshold requirement in the structural analysis, the courts:

• collapsed §112(f) into DOE,
• eliminated the statutory pathway for literal infringement,
• contradicted Graver Tank, Warner‑Jenkinson, Odetics, and WMS Gaming.

7. Why the Issue Matters

If this doctrinal drift is allowed to stand, it would:

• eliminate the statutory pathway for literal infringement under §112(f),
• force patentees to disclose gate‑level circuitry for logic‑design inventions,
• undermine the engineering discipline of logic design,
• create inconsistent outcomes between tribunals,
• and narrow §112(f) to the point of practical extinction.

Procedural Posture

• Federal Circuit judgment entered
• Cert petition deadline: July 22, 2026
• Document repository available July 3, 2026

to be edited

Technical Background — The ’730 Patent and Logic‑Design Structure

1. Overview of the Invention
   • U.S. Patent No. 6,219,730 discloses a logic‑design structure—identified in the specification as Block 34—that performs the dual function of:
     • synchronizing two data streams, and
     • encoding those streams into a unified framed output, all under control of a bit‑rate clock (BCLK).
   • The patent illustrates one implementation of this structure using a gate‑level example (Figure 4A). This example shows how the dual function can be realized using standard logic elements such as flip‑flops, a selector, and timing signals.
2. Gate‑Level Example vs. POSITA Implementation
   • A person of ordinary skill in the art (POSITA) would understand that the gate‑level depiction in Figure 4A is one disclosed embodiment, not a limitation.
   • A POSITA could implement the same dual‑function structure using well‑known integrated‑circuit (IC) technologies, including:
     • ASICs
     • gate arrays
     • programmable logic devices (CPLDs, FPGAs)
     • microcontroller‑based logic
     • VLSI logic blocks
   • These implementations may differ in their internal circuitry, yet a POSITA would recognize them as corresponding structures because they perform the recited dual function as a unified whole, consistent with the specification and without requiring any imported, irrelevant limitations.
   • This engineering flexibility is fundamental to logic‑design practice.
3. Why the Dual Function Matters
   • The claim recites a single, inseparable dual function:
     • synchronizing and encoding (two data streams under control of a bit‑rate clock)
   • A POSITA understands that synchronization and encoding are coordinated operations governed by the same timing signals.
   • This is why the PTAB and the Western District of Washington recognized Block 34 as a complete, enabled structure.
4. Timing Behavior (Figure 4B)
   • Figure 4B illustrates the timing relationships among:
     • the bit‑rate clock (BCLK)
     • the selector signal (SEL)
     • the frame‑start signal (FS)
     • the output bits (QH)
   • These timing diagrams show how the logic‑design structure aligns the two input streams, inserts framing bits, and produces a unified output stream.
5. How §112(f) Relates to the Technical Structure
   • Under §112(f), the analysis requires:
     • identifying the claimed function,
     • identifying the corresponding structure, and
     • determining equivalents of that structure.
   • For the ’730 patent:
     • the function is the dual function of synchronizing and encoding,
     • the corresponding structure is the logic‑design block (Block 34), and
     • equivalent structures include any IC implementation that performs the same dual function in the same overall way.
   • A POSITA would not treat the gate‑level example as limiting.
   • They would recognize that the invention can be implemented using many IC technologies.
6. Why the Technical Background Matters for the Case
   • Understanding the technical structure clarifies why the lower courts erred when they:
     • isolated only the “synchronizing” portion of the dual function,
     • imported additional components not tied to the claim,
     • demanded gate‑level detail, and
     • refused to evaluate the structure as a whole.