TECHNICAL BACKGROUND PAGE

Technical Background — The ’730 Patent and Logic‑Design Structure

1. Overview of the Invention
   • U.S. Patent No. 6,219,730 discloses a logic‑design structure—identified in the specification as Block 34—that performs the dual function of:
     • synchronizing two data streams, and
     • encoding those streams into a unified framed output, all under control of a bit‑rate clock (BCLK).
   • The patent illustrates one implementation of this structure using a gate‑level example (Figure 4A). This example shows how the dual function can be realized using standard logic elements such as flip‑flops, a selector, and timing signals.
2. Gate‑Level Example vs. POSITA Implementation
   • A person of ordinary skill in the art (POSITA) would understand that the gate‑level depiction in Figure 4A is one disclosed embodiment, not a limitation.
   • A POSITA could implement the same dual‑function structure using well‑known integrated‑circuit (IC) technologies, including:
     • ASICs
     • gate arrays
     • programmable logic devices (CPLDs, FPGAs)
     • microcontroller‑based logic
     • VLSI logic blocks
   • These implementations may differ in their internal circuitry, yet a POSITA would recognize them as corresponding structures because they perform the recited dual function as a unified whole, consistent with the specification and without requiring any imported, irrelevant limitations.
   • This engineering flexibility is fundamental to logic‑design practice.
3. Why the Dual Function Matters
   • The claim recites a single, inseparable dual function:
     • synchronizing and encoding (two data streams under control of a bit‑rate clock)
   • A POSITA understands that synchronization and encoding are coordinated operations governed by the same timing signals.
   • This is why the PTAB and the Western District of Washington recognized Block 34 as a complete, enabled structure.
4. Timing Behavior (Figure 4B)
   • Figure 4B illustrates the timing relationships among:
     • the bit‑rate clock (BCLK)
     • the selector signal (SEL)
     • the frame‑start signal (FS)
     • the output bits (QH)
   • These timing diagrams show how the logic‑design structure aligns the two input streams, inserts framing bits, and produces a unified output stream.
5. How §112(f) Relates to the Technical Structure
   • Under §112(f), the analysis requires:
     • identifying the claimed function,
     • identifying the corresponding structure, and
     • determining equivalents of that structure.
   • For the ’730 patent:
     • the function is the dual function of synchronizing and encoding,
     • the corresponding structure is the logic‑design block (Block 34), and
     • equivalent structures include any IC implementation that performs the same dual function in the same overall way.
   • A POSITA would not treat the gate‑level example as limiting.
   • They would recognize that the invention can be implemented using many IC technologies.
6. Why the Technical Background Matters for the Case
   • Understanding the technical structure clarifies why the lower courts erred when they:
     • isolated only the “synchronizing” portion of the dual function,
     • imported additional components not tied to the claim,
     • demanded gate‑level detail, and
     • refused to evaluate the structure as a whole.